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SVF guide statements for multibit flop mapping
July 12, 2024, 11:28 p.m. 3 阅读
In the realm of Logic Equivalence Checking or Functional Netlist ECO, the primary purpose of utilizing the SVF file generated by Synopsys Design Compiler is to facilitate accurate mapping of key points. This is particularly crucial when dealing with designs that involve the utilization of multibit flops. The SVF file is instrumental in conveying how individual flops are combined into multibit flops, as well as elucidating any modifications in instance names.
Netlist Functional ECO to Fix DFT Logic
July 1, 2024, 11:23 p.m. 18 阅读
Netlist functional ECO to fix DFT (Design for Test) logic is a common practice during the chip tape-out stage. Issues that require ECO might include "DFT DRC (Design Rule Check)" , “Missing TDR (Test Data Register)”. Typically, these ECOs are done manually by designers editing large netlists, which is inefficient.
Optimizing ECO Quality: GOF ECO vs. Conformal ECO Methodologies
March 31, 2024, 4:32 p.m. 94 阅读
there exists a crucial distinction between the Implementation Netlist and the Reference Netlist.
Optimizing Metal-Only ECO Efficiency: Leveraging GUI and Automated Approaches
March 4, 2024, 10:19 a.m. 104 阅读
The paramount aspect of Metal-only ECO lies in achieving the final timing. Without achieving timing closure, an ECO cannot be deemed successful.
Integrating Third Party LEC Tool Outcome for Functional ECO
March 1, 2024, 11:46 a.m. 141 阅读
This LEC assessment can seamlessly integrate into GOF ECO for rapid functional ECO iteration. Non-equivalent outcomes may arise from tools such as Synopsys Formality.
Enhancing Functional ECO Precision: Leveraging Pre-Layout Netlist for Accurate Port Phase Detection
Feb. 15, 2024, 10:52 a.m. 82 阅读
In a functional netlist ECO, detecting the boundary phase relationship between the Reference Netlist and the Implementation Netlist is crucial when ports undergo changes.
Accelerating ECOs in SOC Design
Feb. 6, 2024, 11:35 p.m. 129 阅读
When a functional ECO is required, and it pertains to a specific sub-module, the design team aims to restrict the ECO to that particular sub-module rather than initiating synthesis for the entire design.
Create top level full netlist incrementally
Jan. 28, 2024, 10:05 p.m. 94 阅读
Performing a complete top-level netlist synthesis can be time-consuming. GOF provides APIs enabling the integration of newly synthesized sub-modules into the original pre-layout netlist, along with updates to the top-level SVF file.
Navigating Abort Points in Logic Equivalence Checking
Jan. 28, 2024, 9:45 p.m. 79 阅读
Abort points are frequently encountered in Logic Equivalence Checking. LEC tools, which may run for extended periods, might eventually cease operation, leading to an unsuccessful result.
Help file to pass Formality in logic equivalence checking
Jan. 5, 2024, 3:48 p.m. 93 阅读
The difficulty in large netlist ECO arises in successfully navigating logic equivalence checking, especially when undergoing RTL-to-ECO netlist equivalence checking with Formality, and without the aid of an updated SVF file
Convert any Gates to Mux
Jan. 1, 2024, 10:58 p.m. 92 阅读
In some cases, there are designs where only INV, MUX, and Flop types are available as spare gates. However, mapping random ECO logic to MUX-only logic can be a challenge for the synthesis engine. Thankfully, GOF offers a solution to this issue.