http://iccircle.com/column?name=NanDigits NanDigits的IC技术圈专栏 en-us NanDigits版权所有 2026-04-18 05:17:59 2026-04-18 05:17:59 https://iccircle.com/static/image/IC%E6%8A%80%E6%9C%AF%E5%9C%88.jpg https://iccircle.com/column?name=NanDigits https://iccircle.com/column?id=504 Functional Engineering Change Orders (ECOs) are a critical part of the ASIC design flow, often involving complex and iterative changes to a netlist. GOF, a leading EDA tool for functional ECOs, has introduced a groundbreaking feature: GOF AI. By leveraging Large Language Models (LLMs), GOF AI can directly fix netlists, significantly accelerating the ECO process. NanDigits April 6, 2026, 1:37 p.m. https://iccircle.com/column?id=504 https://iccircle.com/column?id=416 In functional netlist ECO, one critical risk often goes unnoticed that DFT logic can be unintentionally broken during ECO implementation. This happens because DFT logic typically remains disabled during ECO operations, and the DFT and ECO flows are managed by different teams using separate methodologies. As a result, verifying and restoring DFT integrity after an ECO can lead to long turnaround times and inefficient iteration cycles. NanDigits Oct. 9, 2025, 12:20 a.m. https://iccircle.com/column?id=416 https://iccircle.com/column?id=395 Artificial Intelligence is evolving rapidly, and its integration into EDA is making netlist ECO flows smarter than ever. With the support of AI agents, highly complex ECO operations can now be executed using simple natural language instructions. This represents a major shift from manual scripting and tedious command writing to an intuitive, AI assisted workflow. NanDigits Oct. 9, 2025, 12:11 a.m. https://iccircle.com/column?id=395 https://iccircle.com/column?id=375 Debugging non-equivalent points in complex IC designs can be a time-consuming task, often requiring users to remember specific API commands and their syntax. GOF addresses this challenge by integrating an AI-powered natural language interface directly into its shell, allowing users to interact with the tool using plain English queries. This significantly streamlines the debugging process, making it more intuitive and efficient. NanDigits July 7, 2025, 1:30 p.m. https://iccircle.com/column?id=375 https://iccircle.com/column?id=374 In the intricate world of Electronic Design Automation (EDA), engineers often face a steep learning curve when mastering complex tools. Remembering every API, its precise syntax, and the nuances of various options can be a significant hurdle, even for experienced users returning after a break. This frequently leads to repetitive consultations of user manuals, diverting valuable time from core design tasks. NanDigits July 7, 2025, 1:23 p.m. https://iccircle.com/column?id=374 https://iccircle.com/column?id=357 For smaller designs, a full re-synthesis can be applied to all three netlist stages. However, the time-intensive nature of a complete automatic ECO run across large designs necessitates a more efficient strategy. GOF ECO addresses this by focusing its automatic ECO capabilities on the initial Synthesis (Pre-layout) Netlist stage. NanDigits May 22, 2025, 11:14 p.m. https://iccircle.com/column?id=357 https://iccircle.com/column?id=341 In modern IC design, the complexity of Design for Test (DFT) flows presents significant challenges. One common issue is the omission of DFT constraints during logic equivalence checking (LEC) and functional netlist ECO. This oversight often results in false non-equivalence reports in LEC and unnecessary modifications in netlist ECO, potentially compromising the integrity of the DFT logic. Given the intricate nature of DFT flows and the diverse tools employed in LEC and netlist ECO, such as Formality for LEC and GOF ECO for netlist modifications, it is challenging to ensure DFT constraints are correctly applied in the initial stages. GOF Debug offers a counter example back-annotation feature that can effectively identify missing DFT constraints, simplifying the debugging process. NanDigits April 15, 2025, 12:42 p.m. https://iccircle.com/column?id=341 https://iccircle.com/column?id=301 A key highlight of this integration is the intelligent AI server, @NanDigits, which is also seamlessly woven into the VS Code experience. @NanDigits acts as an AI-powered assistant, simplifying the often tedious process of ECO script development. NanDigits Feb. 10, 2025, 2:11 p.m. https://iccircle.com/column?id=301 https://iccircle.com/column?id=294 The fast-paced nature of IC design often leads to ECO specifications being delivered as images accompanied by brief textual descriptions. This presents a challenge for implementation teams, who must manually interpret these visuals and translate them into scripts for ECO tools. This manual process is inefficient and susceptible to human error. Our innovative solution leverages AI to automate this process. By directly processing image-based ECO specifications, we eliminate the need for manual interpretation. NanDigits Jan. 15, 2025, 10:29 a.m. https://iccircle.com/column?id=294 https://iccircle.com/column?id=293 GOF ECO provides a streamlined solution for designers to implement functional changes in digital designs without compromising Design for Testability (DFT) functionality. This article highlights the key features of DFT-friendly ECO and the integrated DFT Design Rule Checking (DRC) capabilities within GOF ECO. NanDigits Jan. 15, 2025, 10:21 a.m. https://iccircle.com/column?id=293 https://iccircle.com/column?id=292 Complex IC designs often require multiple steps to debug and verify equivalence between the RTL and gate-level netlists. In these cases, a multi-step LEC approach is essential to ensure accurate results and identify discrepancies effectively. By breaking down the debugging process into distinct stages, each comparison can deal with smaller structural changes. This is especially true when dealing with netlist ECOs involving multibit design. NanDigits Jan. 15, 2025, 10:15 a.m. https://iccircle.com/column?id=292 https://iccircle.com/column?id=272 SVF (Automated setup file) files play a critical role in Logic Equivalence Checking (LEC), particularly in designs involving multibit flops. These files contain essential information about state elements, such as multibit flip-flops mapping, which influence how tools like Synopsys Formality interpret the netlist. When both the Reference and Implementation Netlists contain multibit flops, it's crucial to apply SVF files to each netlist individually to avoid issues. NanDigits Dec. 5, 2024, 6:33 p.m. https://iccircle.com/column?id=272 https://iccircle.com/column?id=181 These stages, such as key point mapping and port inversion checking, are computationally intensive and not easily parallelized, leading to significant processing times. This is where AI comes into play, offering a solution by extracting meaningful patterns from historical ECO data. By learning from past decisions, AI can provide informed guidance during the decision-making process, greatly enhancing efficiency. NanDigits Oct. 12, 2024, 4:09 p.m. https://iccircle.com/column?id=181 https://iccircle.com/column?id=182 The mixed functional ECO flow combines both automatic and manual modes seamlessly to improve the efficiency and quality of functional ECO operations. GOF ECO integrates these two modes, allowing users to perform all ECO-related tasks in one environment without switching between different scripts or netlist files for preprocessing and post-processing. This unification saves time and reduces errors while enabling more control over the changes made to the design. NanDigits Oct. 12, 2024, 4:09 p.m. https://iccircle.com/column?id=182 https://iccircle.com/column?id=176 Mapping random ECO logic to MUX-only logic can be a challenge for the synthesis engine. Thankfully, GOF offers a solution to this issue. NanDigits Sept. 23, 2024, 4:33 p.m. https://iccircle.com/column?id=176 https://iccircle.com/column?id=171 GOF ECO provides a streamlined solution for designers to implement functional changes in digital designs without compromising DFT functionality. This article highlights key features of DFT-friendly ECO and the DFT Design Rule Checking (DRC) capabilities integrated into GOF ECO. NanDigits Sept. 14, 2024, 5:10 p.m. https://iccircle.com/column?id=171 https://iccircle.com/column?id=152 NanDigits, a leading provider of Verilog Netlist ECO and debug tools, is committed to leveraging artificial intelligence (AI) to enhance its technical support, improve the ECO engine, and elevate the user experience. Here's an overview of NanDigits' AI strategy, focusing on its current use, future plans, and measurement of success. NanDigits Aug. 19, 2024, 1:11 p.m. https://iccircle.com/column?id=152 https://iccircle.com/column?id=146 When both the Reference and Implementation Netlists contain multibit flops, it's crucial to apply SVF files to each netlist individually to avoid issues. NanDigits Aug. 11, 2024, 8:58 a.m. https://iccircle.com/column?id=146 https://iccircle.com/column?id=129 In the realm of Logic Equivalence Checking or Functional Netlist ECO, the primary purpose of utilizing the SVF file generated by Synopsys Design Compiler is to facilitate accurate mapping of key points. This is particularly crucial when dealing with designs that involve the utilization of multibit flops. The SVF file is instrumental in conveying how individual flops are combined into multibit flops, as well as elucidating any modifications in instance names. NanDigits July 12, 2024, 11:28 p.m. https://iccircle.com/column?id=129 https://iccircle.com/column?id=118 Netlist functional ECO to fix DFT (Design for Test) logic is a common practice during the chip tape-out stage. Issues that require ECO might include "DFT DRC (Design Rule Check)" , “Missing TDR (Test Data Register)”. Typically, these ECOs are done manually by designers editing large netlists, which is inefficient. NanDigits July 1, 2024, 11:23 p.m. https://iccircle.com/column?id=118 https://iccircle.com/column?id=54 there exists a crucial distinction between the Implementation Netlist and the Reference Netlist. NanDigits March 31, 2024, 4:32 p.m. https://iccircle.com/column?id=54 https://iccircle.com/column?id=41 The paramount aspect of Metal-only ECO lies in achieving the final timing. Without achieving timing closure, an ECO cannot be deemed successful. NanDigits March 4, 2024, 10:19 a.m. https://iccircle.com/column?id=41 https://iccircle.com/column?id=40 This LEC assessment can seamlessly integrate into GOF ECO for rapid functional ECO iteration. Non-equivalent outcomes may arise from tools such as Synopsys Formality. NanDigits March 1, 2024, 11:46 a.m. https://iccircle.com/column?id=40 https://iccircle.com/column?id=36 In a functional netlist ECO, detecting the boundary phase relationship between the Reference Netlist and the Implementation Netlist is crucial when ports undergo changes. NanDigits Feb. 15, 2024, 10:52 a.m. https://iccircle.com/column?id=36 https://iccircle.com/column?id=32 When a functional ECO is required, and it pertains to a specific sub-module, the design team aims to restrict the ECO to that particular sub-module rather than initiating synthesis for the entire design. NanDigits Feb. 6, 2024, 11:35 p.m. https://iccircle.com/column?id=32 https://iccircle.com/column?id=21 Performing a complete top-level netlist synthesis can be time-consuming. GOF provides APIs enabling the integration of newly synthesized sub-modules into the original pre-layout netlist, along with updates to the top-level SVF file. NanDigits Jan. 28, 2024, 10:05 p.m. https://iccircle.com/column?id=21 https://iccircle.com/column?id=20 Abort points are frequently encountered in Logic Equivalence Checking. LEC tools, which may run for extended periods, might eventually cease operation, leading to an unsuccessful result. NanDigits Jan. 28, 2024, 9:45 p.m. https://iccircle.com/column?id=20 https://iccircle.com/column?id=17 The difficulty in large netlist ECO arises in successfully navigating logic equivalence checking, especially when undergoing RTL-to-ECO netlist equivalence checking with Formality, and without the aid of an updated SVF file NanDigits Jan. 5, 2024, 3:48 p.m. https://iccircle.com/column?id=17 https://iccircle.com/column?id=15 In some cases, there are designs where only INV, MUX, and Flop types are available as spare gates. However, mapping random ECO logic to MUX-only logic can be a challenge for the synthesis engine. Thankfully, GOF offers a solution to this issue. NanDigits Jan. 1, 2024, 10:58 p.m. https://iccircle.com/column?id=15