<rss xmlns:atom="http://www.w3.org/2005/Atom" version="2.0">
  <channel>
    <title>IC技术圈</title>
    <link>http://iccircle.com</link>
    <description>IC技术圈</description>
    <atom:link href="http://iccircle.com/feed" rel="self" type="application/rss+xml"></atom:link>
    <language>zh-cn</language>
    <copyright>IC技术圈的小编们共同所有</copyright>
    <lastBuildDate>Tue, 14 Jul 2026 00:20:54 +0800</lastBuildDate>
    <pubDate>Tue, 14 Jul 2026 00:20:54 +0800</pubDate>
    <image>
      <url>https://iccircle.com/static/image/IC%E6%8A%80%E6%9C%AF%E5%9C%88.jpg</url>
      <title>NanDigits的专栏 | IC技术圈</title>
      <link>https://iccircle.com/column?name=NanDigits</link>
    </image>
    
    <item>
      <title>【新版本发布】NanDigits GOF v11.8，SKILL.md</title>
      <link>https://iccircle.com/column?id=528</link>
      <description><![CDATA[你来描述ECO需求，GOF来实现]]></description>
      <author>NanDigits</author>
      <pubDate>Tue, 30 Jun 2026 21:24:33 +0800</pubDate>
      <guid isPermaLink="true">https://iccircle.com/column?id=528</guid>
    </item>
    
    <item>
      <title>数字后端APR如何撒sparecell？</title>
      <link>https://iccircle.com/column?id=524</link>
      <description><![CDATA[以 innovus 为例，createSpareModule 创建 spare cell module 后，用placeSpareModule 来撒 spare cell。来看一下它他命令参数。]]></description>
      <author>NanDigits</author>
      <pubDate>Tue, 23 Jun 2026 18:22:10 +0800</pubDate>
      <guid isPermaLink="true">https://iccircle.com/column?id=524</guid>
    </item>
    
    <item>
      <title>GOF AI Revolutionizes Functional ECO: Direct Netlist Fixes with LLM Intelligence</title>
      <link>https://iccircle.com/column?id=504</link>
      <description><![CDATA[Functional Engineering Change Orders (ECOs) are a critical part of the ASIC design flow, often involving complex and iterative changes to a netlist. GOF, a leading EDA tool for functional ECOs, has introduced a groundbreaking feature: GOF AI. By leveraging Large Language Models (LLMs), GOF AI can directly fix netlists, significantly accelerating the ECO process.]]></description>
      <author>NanDigits</author>
      <pubDate>Mon, 06 Apr 2026 13:37:33 +0800</pubDate>
      <guid isPermaLink="true">https://iccircle.com/column?id=504</guid>
    </item>
    
    <item>
      <title>Ensuring DFT Integrity in Functional Netlist ECO with GOF ECO</title>
      <link>https://iccircle.com/column?id=416</link>
      <description><![CDATA[In functional netlist ECO, one critical risk often goes unnoticed that DFT logic can be unintentionally broken during ECO implementation. This happens because DFT logic typically remains disabled during ECO operations, and the DFT and ECO flows are managed by different teams using separate methodologies. As a result, verifying and restoring DFT integrity after an ECO can lead to long turnaround times and inefficient iteration cycles.]]></description>
      <author>NanDigits</author>
      <pubDate>Thu, 09 Oct 2025 00:20:38 +0800</pubDate>
      <guid isPermaLink="true">https://iccircle.com/column?id=416</guid>
    </item>
    
    <item>
      <title>AI-Driven ECO: From Natural Language to Automated Complex Operations</title>
      <link>https://iccircle.com/column?id=395</link>
      <description><![CDATA[Artificial Intelligence is evolving rapidly, and its integration into EDA is making netlist ECO flows smarter than ever. With the support of AI agents, highly complex ECO operations can now be executed using simple natural language instructions. This represents a major shift from manual scripting and tedious command writing to an intuitive, AI assisted workflow.]]></description>
      <author>NanDigits</author>
      <pubDate>Thu, 09 Oct 2025 00:11:09 +0800</pubDate>
      <guid isPermaLink="true">https://iccircle.com/column?id=395</guid>
    </item>
    
    <item>
      <title>Natural Language Debugging in GOF Shell</title>
      <link>https://iccircle.com/column?id=375</link>
      <description><![CDATA[Debugging non-equivalent points in complex IC designs can be a time-consuming task, often requiring users to remember specific API commands and their syntax. GOF addresses this challenge by integrating an AI-powered natural language interface directly into its shell, allowing users to interact with the tool using plain English queries. This significantly streamlines the debugging process, making it more intuitive and efficient.]]></description>
      <author>NanDigits</author>
      <pubDate>Mon, 07 Jul 2025 13:30:14 +0800</pubDate>
      <guid isPermaLink="true">https://iccircle.com/column?id=375</guid>
    </item>
    
    <item>
      <title>AI-Powered Natural Language ECO: Revolutionizing Netlist Modifications</title>
      <link>https://iccircle.com/column?id=374</link>
      <description><![CDATA[In the intricate world of Electronic Design Automation (EDA), engineers often face a steep learning curve when mastering complex tools. Remembering every API, its precise syntax, and the nuances of various options can be a significant hurdle, even for experienced users returning after a break. This frequently leads to repetitive consultations of user manuals, diverting valuable time from core design tasks.]]></description>
      <author>NanDigits</author>
      <pubDate>Mon, 07 Jul 2025 13:23:22 +0800</pubDate>
      <guid isPermaLink="true">https://iccircle.com/column?id=374</guid>
    </item>
    
    <item>
      <title>Streamlining ECO with Intelligent Script Application in GOF ECO</title>
      <link>https://iccircle.com/column?id=357</link>
      <description><![CDATA[For smaller designs, a full re-synthesis can be applied to all three netlist stages. However, the time-intensive nature of a complete automatic ECO run across large designs necessitates a more efficient strategy. GOF ECO addresses this by focusing its automatic ECO capabilities on the initial Synthesis (Pre-layout) Netlist stage.]]></description>
      <author>NanDigits</author>
      <pubDate>Thu, 22 May 2025 23:14:23 +0800</pubDate>
      <guid isPermaLink="true">https://iccircle.com/column?id=357</guid>
    </item>
    
    <item>
      <title>Fast Pinpointing Missing DFT Constraints Using GOF Debug Counter Example Back-Annotation</title>
      <link>https://iccircle.com/column?id=341</link>
      <description><![CDATA[In modern IC design, the complexity of Design for Test (DFT) flows presents significant challenges. One common issue is the omission of DFT constraints during logic equivalence checking (LEC) and functional netlist ECO. This oversight often results in false non-equivalence reports in LEC and unnecessary modifications in netlist ECO, potentially compromising the integrity of the DFT logic. Given the intricate nature of DFT flows and the diverse tools employed in LEC and netlist ECO, such as Formality for LEC and GOF ECO for netlist modifications, it is challenging to ensure DFT constraints are correctly applied in the initial stages. GOF Debug offers a counter example back-annotation feature that can effectively identify missing DFT constraints, simplifying the debugging process.]]></description>
      <author>NanDigits</author>
      <pubDate>Tue, 15 Apr 2025 12:42:51 +0800</pubDate>
      <guid isPermaLink="true">https://iccircle.com/column?id=341</guid>
    </item>
    
    <item>
      <title>Boosting Productivity: AI-Powered ECO Scripting in VS Code with the GOF Platform</title>
      <link>https://iccircle.com/column?id=301</link>
      <description><![CDATA[A key highlight of this integration is the intelligent AI server, @NanDigits, which is also seamlessly woven into the VS Code experience. @NanDigits acts as an AI-powered assistant, simplifying the often tedious process of ECO script development.]]></description>
      <author>NanDigits</author>
      <pubDate>Mon, 10 Feb 2025 14:11:31 +0800</pubDate>
      <guid isPermaLink="true">https://iccircle.com/column?id=301</guid>
    </item>
    
    <item>
      <title>Streamlining Netlist ECO with AI-Powered Image Processing</title>
      <link>https://iccircle.com/column?id=294</link>
      <description><![CDATA[The fast-paced nature of IC design often leads to ECO specifications being delivered as images accompanied by brief textual descriptions. This presents a challenge for implementation teams, who must manually interpret these visuals and translate them into scripts for ECO tools. This manual process is inefficient and susceptible to human error. Our innovative solution leverages AI to automate this process. By directly processing image-based ECO specifications, we eliminate the need for manual interpretation.]]></description>
      <author>NanDigits</author>
      <pubDate>Wed, 15 Jan 2025 10:29:25 +0800</pubDate>
      <guid isPermaLink="true">https://iccircle.com/column?id=294</guid>
    </item>
    
    <item>
      <title>Streamlining Functional Changes with DFT-Aware ECO in GOF ECO</title>
      <link>https://iccircle.com/column?id=293</link>
      <description><![CDATA[GOF ECO provides a streamlined solution for designers to implement functional changes in digital designs without compromising Design for Testability (DFT) functionality. This article highlights the key features of DFT-friendly ECO and the integrated DFT Design Rule Checking (DRC) capabilities within GOF ECO.]]></description>
      <author>NanDigits</author>
      <pubDate>Wed, 15 Jan 2025 10:21:53 +0800</pubDate>
      <guid isPermaLink="true">https://iccircle.com/column?id=293</guid>
    </item>
    
    <item>
      <title>Multi-Step LEC for Complex Functional ECO Debugging</title>
      <link>https://iccircle.com/column?id=292</link>
      <description><![CDATA[Complex IC designs often require multiple steps to debug and verify equivalence between the RTL and gate-level netlists. In these cases, a multi-step LEC approach is essential to ensure accurate results and identify discrepancies effectively. By breaking down the debugging process into distinct stages, each comparison can deal with smaller structural changes. This is especially true when dealing with netlist ECOs involving multibit design.]]></description>
      <author>NanDigits</author>
      <pubDate>Wed, 15 Jan 2025 10:15:28 +0800</pubDate>
      <guid isPermaLink="true">https://iccircle.com/column?id=292</guid>
    </item>
    
    <item>
      <title>SVF Files for Multibit Flop Design and Hidden Rules</title>
      <link>https://iccircle.com/column?id=272</link>
      <description><![CDATA[SVF (Automated setup file) files play a critical role in Logic Equivalence Checking (LEC), particularly in designs involving multibit flops. These files contain essential information about state elements, such as multibit flip-flops mapping, which influence how tools like Synopsys Formality interpret the netlist. When both the Reference and Implementation Netlists contain multibit flops, it&#x27;s crucial to apply SVF files to each netlist individually to avoid issues.]]></description>
      <author>NanDigits</author>
      <pubDate>Thu, 05 Dec 2024 18:33:21 +0800</pubDate>
      <guid isPermaLink="true">https://iccircle.com/column?id=272</guid>
    </item>
    
    <item>
      <title>AI-Assisted ECO Decision-Making</title>
      <link>https://iccircle.com/column?id=181</link>
      <description><![CDATA[These stages, such as key point mapping and port inversion checking,  are computationally intensive and not easily parallelized, leading to significant processing times. This is where AI comes into play, offering a solution by extracting meaningful patterns from historical ECO data. By learning from past decisions, AI can provide informed guidance during the decision-making process, greatly enhancing efficiency.]]></description>
      <author>NanDigits</author>
      <pubDate>Sat, 12 Oct 2024 16:09:56 +0800</pubDate>
      <guid isPermaLink="true">https://iccircle.com/column?id=181</guid>
    </item>
    
    <item>
      <title>Optimizing ECO Efficiency: A Seamless Integration of Manual and Automatic Flows</title>
      <link>https://iccircle.com/column?id=182</link>
      <description><![CDATA[The mixed functional ECO flow combines both automatic and manual modes seamlessly to improve the efficiency and quality of functional ECO operations. GOF ECO integrates these two modes, allowing users to perform all ECO-related tasks in one environment without switching between different scripts or netlist files for preprocessing and post-processing. This unification saves time and reduces errors while enabling more control over the changes made to the design.]]></description>
      <author>NanDigits</author>
      <pubDate>Sat, 12 Oct 2024 16:09:37 +0800</pubDate>
      <guid isPermaLink="true">https://iccircle.com/column?id=182</guid>
    </item>
    
    <item>
      <title>Efficient Spare Gate Mapping in Metal-Only ECO: Converting ECO Logic to MUX-Only Logic</title>
      <link>https://iccircle.com/column?id=176</link>
      <description><![CDATA[Mapping random ECO logic to MUX-only logic can be a challenge for the synthesis engine. Thankfully, GOF offers a solution to this issue.]]></description>
      <author>NanDigits</author>
      <pubDate>Mon, 23 Sep 2024 16:33:40 +0800</pubDate>
      <guid isPermaLink="true">https://iccircle.com/column?id=176</guid>
    </item>
    
    <item>
      <title>DFT DRC and script automation</title>
      <link>https://iccircle.com/column?id=171</link>
      <description><![CDATA[GOF ECO provides a streamlined solution for designers to implement functional changes in digital designs without compromising DFT functionality. This article highlights key features of DFT-friendly ECO and the DFT Design Rule Checking (DRC) capabilities integrated into GOF ECO.]]></description>
      <author>NanDigits</author>
      <pubDate>Sat, 14 Sep 2024 17:10:44 +0800</pubDate>
      <guid isPermaLink="true">https://iccircle.com/column?id=171</guid>
    </item>
    
    <item>
      <title>AI Strategy in Netlist ECO</title>
      <link>https://iccircle.com/column?id=152</link>
      <description><![CDATA[NanDigits, a leading provider of Verilog Netlist ECO and debug tools, is committed to leveraging artificial intelligence (AI) to enhance its technical support, improve the ECO engine, and elevate the user experience. Here&#x27;s an overview of NanDigits&#x27; AI strategy, focusing on its current use, future plans, and measurement of success.]]></description>
      <author>NanDigits</author>
      <pubDate>Mon, 19 Aug 2024 13:11:48 +0800</pubDate>
      <guid isPermaLink="true">https://iccircle.com/column?id=152</guid>
    </item>
    
    <item>
      <title>Why Gate-to-Gate Comparison Fails in Formality with Multibit Flops?</title>
      <link>https://iccircle.com/column?id=146</link>
      <description><![CDATA[When both the Reference and Implementation Netlists contain multibit flops, it&#x27;s crucial to apply SVF files to each netlist individually to avoid issues.]]></description>
      <author>NanDigits</author>
      <pubDate>Sun, 11 Aug 2024 08:58:40 +0800</pubDate>
      <guid isPermaLink="true">https://iccircle.com/column?id=146</guid>
    </item>
    
    <item>
      <title>SVF guide statements for multibit flop mapping</title>
      <link>https://iccircle.com/column?id=129</link>
      <description><![CDATA[In the realm of Logic Equivalence Checking or Functional Netlist ECO, the primary purpose of utilizing the SVF file generated by Synopsys Design Compiler is to facilitate accurate mapping of key points. This is particularly crucial when dealing with designs that involve the utilization of multibit flops. The SVF file is instrumental in conveying how individual flops are combined into multibit flops, as well as elucidating any modifications in instance names.]]></description>
      <author>NanDigits</author>
      <pubDate>Fri, 12 Jul 2024 23:28:19 +0800</pubDate>
      <guid isPermaLink="true">https://iccircle.com/column?id=129</guid>
    </item>
    
    <item>
      <title>Netlist Functional ECO to Fix DFT Logic</title>
      <link>https://iccircle.com/column?id=118</link>
      <description><![CDATA[Netlist functional ECO to fix DFT (Design for Test) logic is a common practice during the chip tape-out stage. Issues that require ECO might include &quot;DFT DRC (Design Rule Check)&quot; , “Missing TDR (Test Data Register)”. Typically, these ECOs are done manually by designers editing large netlists, which is inefficient.]]></description>
      <author>NanDigits</author>
      <pubDate>Mon, 01 Jul 2024 23:23:08 +0800</pubDate>
      <guid isPermaLink="true">https://iccircle.com/column?id=118</guid>
    </item>
    
    <item>
      <title>Optimizing ECO Quality: GOF ECO vs. Conformal ECO Methodologies</title>
      <link>https://iccircle.com/column?id=54</link>
      <description><![CDATA[there exists a crucial distinction between the Implementation Netlist and the Reference Netlist.]]></description>
      <author>NanDigits</author>
      <pubDate>Sun, 31 Mar 2024 16:32:22 +0800</pubDate>
      <guid isPermaLink="true">https://iccircle.com/column?id=54</guid>
    </item>
    
    <item>
      <title>Optimizing Metal-Only ECO Efficiency: Leveraging GUI and Automated Approaches</title>
      <link>https://iccircle.com/column?id=41</link>
      <description><![CDATA[The paramount aspect of Metal-only ECO lies in achieving the final timing. Without achieving timing closure, an ECO cannot be deemed successful.]]></description>
      <author>NanDigits</author>
      <pubDate>Mon, 04 Mar 2024 10:19:25 +0800</pubDate>
      <guid isPermaLink="true">https://iccircle.com/column?id=41</guid>
    </item>
    
    <item>
      <title>Integrating Third Party LEC Tool Outcome for Functional ECO</title>
      <link>https://iccircle.com/column?id=40</link>
      <description><![CDATA[This LEC assessment can seamlessly integrate into GOF ECO for rapid functional ECO iteration. Non-equivalent outcomes may arise from tools such as Synopsys Formality.]]></description>
      <author>NanDigits</author>
      <pubDate>Fri, 01 Mar 2024 11:46:23 +0800</pubDate>
      <guid isPermaLink="true">https://iccircle.com/column?id=40</guid>
    </item>
    
    <item>
      <title>Enhancing Functional ECO Precision: Leveraging Pre-Layout Netlist for Accurate Port Phase Detection</title>
      <link>https://iccircle.com/column?id=36</link>
      <description><![CDATA[In a functional netlist ECO, detecting the boundary phase relationship between the Reference Netlist and the Implementation Netlist is crucial when ports undergo changes.]]></description>
      <author>NanDigits</author>
      <pubDate>Thu, 15 Feb 2024 10:52:27 +0800</pubDate>
      <guid isPermaLink="true">https://iccircle.com/column?id=36</guid>
    </item>
    
    <item>
      <title>Accelerating ECOs in SOC Design</title>
      <link>https://iccircle.com/column?id=32</link>
      <description><![CDATA[When a functional ECO is required, and it pertains to a specific sub-module, the design team aims to restrict the ECO to that particular sub-module rather than initiating synthesis for the entire design.]]></description>
      <author>NanDigits</author>
      <pubDate>Tue, 06 Feb 2024 23:35:34 +0800</pubDate>
      <guid isPermaLink="true">https://iccircle.com/column?id=32</guid>
    </item>
    
    <item>
      <title>Create top level full netlist incrementally</title>
      <link>https://iccircle.com/column?id=21</link>
      <description><![CDATA[Performing a complete top-level netlist synthesis can be time-consuming. GOF provides APIs enabling the integration of newly synthesized sub-modules into the original pre-layout netlist, along with updates to the top-level SVF file.]]></description>
      <author>NanDigits</author>
      <pubDate>Sun, 28 Jan 2024 22:05:11 +0800</pubDate>
      <guid isPermaLink="true">https://iccircle.com/column?id=21</guid>
    </item>
    
    <item>
      <title>Navigating Abort Points in Logic Equivalence Checking</title>
      <link>https://iccircle.com/column?id=20</link>
      <description><![CDATA[Abort points are frequently encountered in Logic Equivalence Checking. LEC tools, which may run for extended periods, might eventually cease operation, leading to an unsuccessful result.]]></description>
      <author>NanDigits</author>
      <pubDate>Sun, 28 Jan 2024 21:45:51 +0800</pubDate>
      <guid isPermaLink="true">https://iccircle.com/column?id=20</guid>
    </item>
    
    <item>
      <title>Help file to pass Formality in logic equivalence checking</title>
      <link>https://iccircle.com/column?id=17</link>
      <description><![CDATA[The difficulty in large netlist ECO arises in successfully navigating logic equivalence checking, especially when undergoing RTL-to-ECO netlist equivalence checking with Formality, and without the aid of an updated SVF file]]></description>
      <author>NanDigits</author>
      <pubDate>Fri, 05 Jan 2024 15:48:23 +0800</pubDate>
      <guid isPermaLink="true">https://iccircle.com/column?id=17</guid>
    </item>
    
  </channel>
</rss>
