Netlist functional ECO to fix DFT (Design for Test) logic is a common practice during the chip tape-out stage. Issues that require ECO might include:

• DFT DRC (Design Rule Check) C6: This could be due to a missing clock multiplexer for the DFT clock.

• Missing TDR (Test Data Register): Certain control signals might be missing TDRs.

Typically, these ECOs are done manually by designers editing large netlists, which is inefficient. The GOF platform supports both GUI/script-aided manual ECO and fully automated ECO.

GUI and Script-aided ECO helps designers focus on specific logic points causing DFT failures. An example of manual ECO can be found here.

This article presents an automatic method for performing DFT ECO using the GOF ECO platform.

Overview

In the automatic DFT ECO process, DFT logic that is disabled in the functional netlist ECO by setting constraints must have those constraints removed to repair the DFT logic. The Reference Netlist's DFT logic serves as a guide for repairing the Implementation Netlist. The automatic ECO process only addresses DFT logic with fixed naming conventions. In complex DFT designs, DFT tools might add flip-flops (flops) with random naming styles, such as those found in IEEE 1500 wrapper cell features. For such designs, users may need to rely on GUI and Script-aided manual ECOs to make changes to the DFT logic.

DFT ECO Process

During the DFT logic insertion stage, the DFT scripts have been enhanced with new features, such as the addition of a TDR register. The DFT tool integrates the new DFT logic into the design, and the resulting netlist, including this updated DFT logic, is saved as the Reference Netlist.

The GOF ECO script reads this Reference Netlist to repair the Implementation Netlist. Below is a detailed script for automatic DFT ECO:

# GOF ECO script, run_dft_auto.pl
use strict;
setup_eco("eco_dft_auto");# Setup ECO name
read_library("art.5nm.lib");# Read in standard library
read_svf("-ref", "reference.svf.txt");       # Optional, must be loaded before read_design, must be in text format
read_svf("-imp", "implementation.svf.txt");  # Optional, must be loaded before read_design, must be in text format
read_design("-ref", "dft_new_ref.gv");# Read in Reference Netlist with new DFT
read_design("-imp", "postnetlist_old_dft.gv");# Read in Implementation Netlist Which is under ECO
set_top("top_wrapper");# Set the top module
fix_design;
report_eco(); # ECO report
write_verilog("imp_dft_eco.gv");# Write out ECO result in Verilog
exit; # Exit when the ECO is done, comment it out to go to interactive mode when 'GOF >' appears

After the automatic ECO is completed, the TDR from the new reference netlist is correctly inserted into the implementation netlist. The following figure illustrates the DFT logic with one TDR register added and four new instances included in the ECO. Subsequently, a DFT simulation should be run to verify that the modified implementation netlist performs the desired DFT functions.

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