Our previous example showed how combining manual and automatic ECO reduced a patch’s gate count. This example looks at a different issue: the type and location of the spare cells available to implement it.

用 GOF 用户手册中的 DFT DRC 示例，说明如何从报错实例进入原理图，找到改动点，再在同一原理图中完成 ECO。

记录用 Hermes Agent(Nous Research 开源 AI Agent)搭配 Kimi K3 模型和 gof-ai skill，跑通 GOF 功能 ECO 工具自带 ai_eco 例程的全过程。内容涵盖整体架构、自然语言 spec 直达 ECO 流程的执行步骤、事前环境准备清单(tmux/xterm、Python venv 隔离、DISPLAY 检查)，以及最终 ECO 修复结果。对想用 AI Agent 自动化 EDA 流程的工程师有参考价值。

本文基于实战经验，梳理出一份功能ECO后中后端工程师需要**重做（Must）**、**视情况重做（Optional）**以及**重点关注**的复查清单，希望能为相关从业者提供一份清晰的实操参考。

你来描述ECO需求，GOF来实现。首个为AI时代打造的网表ECO平台。支持自然语言式ECO、AI驱动的非等价性调试，以及从规格到RTL的自动生成——这一切均建立在超过15年经过量产验证的ECO技术之上。

你来描述ECO需求，GOF来实现

以 innovus 为例，createSpareModule 创建 spare cell module 后，用placeSpareModule 来撒 spare cell。来看一下它他命令参数。

Functional Engineering Change Orders (ECOs) are a critical part of the ASIC design flow, often involving complex and iterative changes to a netlist. GOF, a leading EDA tool for functional ECOs, has introduced a groundbreaking feature: GOF AI. By leveraging Large Language Models (LLMs), GOF AI can directly fix netlists, significantly accelerating the ECO process.

In functional netlist ECO, one critical risk often goes unnoticed that DFT logic can be unintentionally broken during ECO implementation. This happens because DFT logic typically remains disabled during ECO operations, and the DFT and ECO flows are managed by different teams using separate methodologies. As a result, verifying and restoring DFT integrity after an ECO can lead to long turnaround times and inefficient iteration cycles.

Artificial Intelligence is evolving rapidly, and its integration into EDA is making netlist ECO flows smarter than ever. With the support of AI agents, highly complex ECO operations can now be executed using simple natural language instructions. This represents a major shift from manual scripting and tedious command writing to an intuitive, AI assisted workflow.

Debugging non-equivalent points in complex IC designs can be a time-consuming task, often requiring users to remember specific API commands and their syntax. GOF addresses this challenge by integrating an AI-powered natural language interface directly into its shell, allowing users to interact with the tool using plain English queries. This significantly streamlines the debugging process, making it more intuitive and efficient.

In the intricate world of Electronic Design Automation (EDA), engineers often face a steep learning curve when mastering complex tools. Remembering every API, its precise syntax, and the nuances of various options can be a significant hurdle, even for experienced users returning after a break. This frequently leads to repetitive consultations of user manuals, diverting valuable time from core design tasks.

For smaller designs, a full re-synthesis can be applied to all three netlist stages. However, the time-intensive nature of a complete automatic ECO run across large designs necessitates a more efficient strategy. GOF ECO addresses this by focusing its automatic ECO capabilities on the initial Synthesis (Pre-layout) Netlist stage.

In modern IC design, the complexity of Design for Test (DFT) flows presents significant challenges. One common issue is the omission of DFT constraints during logic equivalence checking (LEC) and functional netlist ECO. This oversight often results in false non-equivalence reports in LEC and unnecessary modifications in netlist ECO, potentially compromising the integrity of the DFT logic. Given the intricate nature of DFT flows and the diverse tools employed in LEC and netlist ECO, such as Formality for LEC and GOF ECO for netlist modifications, it is challenging to ensure DFT constraints are correctly applied in the initial stages. GOF Debug offers a counter example back-annotation feature that can effectively identify missing DFT constraints, simplifying the debugging process.

A key highlight of this integration is the intelligent AI server, @NanDigits, which is also seamlessly woven into the VS Code experience. @NanDigits acts as an AI-powered assistant, simplifying the often tedious process of ECO script development.

The fast-paced nature of IC design often leads to ECO specifications being delivered as images accompanied by brief textual descriptions. This presents a challenge for implementation teams, who must manually interpret these visuals and translate them into scripts for ECO tools. This manual process is inefficient and susceptible to human error. Our innovative solution leverages AI to automate this process. By directly processing image-based ECO specifications, we eliminate the need for manual interpretation.

GOF ECO provides a streamlined solution for designers to implement functional changes in digital designs without compromising Design for Testability (DFT) functionality. This article highlights the key features of DFT-friendly ECO and the integrated DFT Design Rule Checking (DRC) capabilities within GOF ECO.

Complex IC designs often require multiple steps to debug and verify equivalence between the RTL and gate-level netlists. In these cases, a multi-step LEC approach is essential to ensure accurate results and identify discrepancies effectively. By breaking down the debugging process into distinct stages, each comparison can deal with smaller structural changes. This is especially true when dealing with netlist ECOs involving multibit design.

SVF (Automated setup file) files play a critical role in Logic Equivalence Checking (LEC), particularly in designs involving multibit flops. These files contain essential information about state elements, such as multibit flip-flops mapping, which influence how tools like Synopsys Formality interpret the netlist. When both the Reference and Implementation Netlists contain multibit flops, it's crucial to apply SVF files to each netlist individually to avoid issues.

The mixed functional ECO flow combines both automatic and manual modes seamlessly to improve the efficiency and quality of functional ECO operations. GOF ECO integrates these two modes, allowing users to perform all ECO-related tasks in one environment without switching between different scripts or netlist files for preprocessing and post-processing. This unification saves time and reduces errors while enabling more control over the changes made to the design.