A functional ECO patch may look small in the netlist. After place and route, another question matters: can the change be implemented with the spare resources already in the design?
Our previous example showed how combining manual and automatic ECO reduced a patch’s gate count. This example looks at a different issue: the type and location of the spare cells available to implement it.
In a documented NanDigits experiment, the design contains both standard spare cells and metal-configurable gate-array spare cells. This allows us to compare two implementations of the ECO.
Standard spare cells already provide particular logic functions. A patch needs compatible functions, sufficient resources, and usable locations. Gate-array spare cells provide pre-placed resources that can be configured through the supported metal-layer changes to implement compatible functional cells.
This flexibility depends on the library and the available tile resources. An ordinary filler cell cannot simply be assumed to support a metal-configurable logic function.
Figure 1. Resources in the experimental design: gate-array spares in green and standard spares in red. Gate-array resources are more numerous in this setup; this is part of the comparison’s context.
Gate-array resources: Approximately 70 gate-array functional cells; a more concentrated affected region.
Standard spare cells: Approximately 90 spare gates; used resources spread over a larger region.
Figure 2. Connection view for the gate-array ECO implementation. These lines illustrate connectivity, rather than a signed-off routed result.
The cell counts describe different mapped implementations. They do not establish an equal-area or equal-timing comparison, and they should not be read as a general percentage improvement for gate-array ECO.
Figure 3. In this example, the red gate-array ECO region is more concentrated than the blue standard-spare ECO region. This figure uses different colors from Figure 1.
A spare gate can implement the right function and still be inconveniently located. Looking at the affected region and the available resources helps engineers assess the physical work that remains after patch generation.
GOF supports mapping gate-array functional cells to compatible spare resources using library and physical information. The useful question is whether the resulting mapping fits this design’s available resources and implementation requirements.
The figures show a more concentrated solution in this test. They do not, by themselves, prove shorter routed wirelength, better timing, lower power, or a faster sign-off cycle.
Start with the supported library cells and permitted metal changes. Then inspect the spare-cell types, tile capacity, distribution, and proximity to the changed logic. A dense supply of configurable resources can create options that a sparse set of fixed-function gates cannot offer.
After mapping, check the written-out netlist and complete the project’s required equivalence, timing, routing, DRC, and DFT checks. GOF LEC can support development checks; final sign-off follows the customer’s qualified flow.
The lesson from this example is practical: evaluate an ECO patch together with the spare resources that will implement it. Gate count is one part of that decision. Resource compatibility and location are another.
When reviewing a metal-only ECO, what becomes the blocker first: spare-cell function, available capacity, or location?
