来源：https://www.eetimes.com/how-ai-will-define-the-next-silicon-supercycle
Silicon technologies define the billions of devices we use today, as well as powering solutions in the data center and cloud that are vital for processing in the age of AI. However, with the meteoric rise of AI creating yet more demand for compute and ongoing push for smaller processing nodes, the cost and complexity of chips continue to rise at an unprecedented rate.
In fact, according to McKinsey estimates, the total generative AI compute demand could reach 25×1030 FLOPs by 2030, which vastly exceeds the performance of current supercomputers and AI systems. Therefore, efficient AI processing through silicon remains a core consideration for the industry.
As a result, the semiconductor industry currently sits at an inflection point that will ultimately require a transformation in silicon design, development and deployment. The next big silicon supercycle will unleash life-changing innovation and decades of unprecedented engineering creativity.
Here are my seven predictions for how this will happen:
From a cost and physics perspective, traditional silicon tape-outs are becoming increasingly difficult. Today, they are extraordinarily expensive, with the push towards even smaller processing nodes, like 2 nm, adding further complexity and costs during manufacturing. This is alongside continuous demands for more compute in the age of AI.
The end result is even more complex chip designs that will not be possible to achieve if the industry continues with “business as usual.” Therefore, the semiconductor industry needs to think beyond traditional silicon design approaches and explore new, creative ways to tackle these current challenges and drive continuous technology innovation. One such approach is chiplets.
There is a realization within the semiconductor industry that core silicon components do not need to be integrated on a single, monolithic chip. Chiplets are one solution, as it allows the stacking and interconnection of multiple semiconductor dies to increase performance, improve efficiency and create interesting new design possibilities, like die-to-die interfaces and new 2.5D and 3D packaging solutions.
Instead of designing a new chip, silicon manufacturers can add more chiplets to increase computational power and performance, or even upgrade existing chiplets, to bring new products to market faster. Chiplets are also easier to manufacture than single monolithic chips, creating less waste during the manufacturing process.
All of these benefits could make chiplets a potential game-changer for silicon design, development and deployment. As a result, the different implementation techniques of chiplets are getting more attention and beginning to have an impact on core architecture and micro-architecture. In the immediate future, architects will need to be aware of what different chiplet implementations offer, whether it is the manufacturing process node or packaging technology, so they can take advantage of the performance and efficiency benefits.
By following Moore’s Law, the industry has put billions of transistors on a chip, doubled performance and halved power every year. However, this continuous push for more transistors, more performance and less power on a single, monolithic chip is simply not sustainable. The semiconductor industry will need to rethink and recalibrate Moore’s Law. In fact, foundry and packaging companies are already finding new ways to push the boundaries of Moore’s Law but under new dimensions, with chiplets being one solution.
Part of this Moore’s Law recalibration is moving away from solely focusing on performance as the key metric and instead valuing performance per watt, performance per area, performance per power and total cost of ownership as core metrics during silicon design. These metrics are more relevant to where the wider tech industry is heading, as it pushes for more efficient computing for AI workloads.
The industry-wide drive for efficient computing in AI is covering all technology touchpoints, from the big data centers to the edge—the actual devices. At the heart of this push will be innovative new silicon designs with power efficiency at the core.
Finding ways to limit the power consumption of the world’s large data centers is paramount, especially when you consider that they require 460 TWh of electricity annually—the equivalent to the entire country of Germany. Introducing larger data centers will consume yet more energy and power, creating AI sustainability challenges both for businesses and the planet.
Fortunately, we know that much of the industry is already demanding more efficient AI. The world’s leading technology companies, including Amazon, Google, Microsoft and Oracle, are already adopting power-efficient technologies for their own optimized silicon designs for cloud data centers.
A significant part of the push for efficient AI is optimized silicon, which will continue to grow. Whereas many of the current SoCs are general-purpose chipsets, optimized silicon is designed to meet specific requirements for a particular market, application or customer.
Almost everyone involved in the semiconductor industry is exploring and investing in optimized silicon, particularly the “big four” cloud hyperscalers, including AWS, Google Cloud and Microsoft, who are responsible for nearly half of the $100 billion spent on cloud servers every year.
However, optimized silicon is not just for the big cloud hyperscalers. Smaller companies are creating their own solutions to meet a variety of complex computing requirements. For example, Faraday Technology, an emerging fabless technology provider, is developing its own 64-core optimized silicon SoC for data centers and advanced 5G networks, which is supported by Arm and Intel Foundry Services.
The push towards optimized silicon will help tech companies deliver true commercial differentiation in their solutions. Compute subsystems are core computing components that enable partners to differentiate and customize their own solutions, as each is configured to perform or contribute towards specific computing functions or specialized functionalities.
A great example is Korean-based Rebellions, which recently announced the development of a new large-scale AI platform, the REBEL AI platform, to drive power efficiency for AI workloads. The platform is built on Arm Neoverse Compute Subsystems V3, but also leverages 2-nm process node and packaging from Samsung Foundry and design services from ADTechnology to deliver a differentiated product for the market.
The unprecedented engineering complexity that we are seeing with the new era of silicon will require specific expertise from different companies at every stage of silicon design, development and deployment. No one company alone will be able to cover every single level of design and integration, with deep levels of ecosystem collaboration needed. This provides unique opportunities for different companies to deliver different computing components and solutions based on their core competencies.
Collaborations, such as Arm’s Total Design, can help empower an ecosystem to accelerate the development and deployment of silicon solutions and systems that are more effective, efficient and performant. Augmenting different solutions and layers of expertise from across the technology ecosystem will enable the next generation of differentiated and powerful silicon designs.
The next decade promises to be a truly exciting time for silicon innovation, leading to new design possibilities that will transform the wider tech industry. However, one thing is clear: business as usual is not sustainable in the long term, especially when you consider the complex computing challenges that the industry is facing.
Through a rethink of silicon design, a renewed focus on power-efficient AI processing and unprecedented ecosystem collaborations, the semiconductor industry will put itself at the center of the ongoing computing transformation for the age of AI.
