Integrated IR Shift-left Solution & Improved Coverage in Construction with RedHawk-Fusion
PRO-ME:Postroute Resource Optimization with Merging ECOs of Multiple Instantiated Blocks
Achieve Faster Root Cause Analysis of Synthesis-Optimized Registers early at RTL
Catching unwanted synthesis optimization on RTL anchor points
Synopsys Fusion Compiler Enhancements for Improved Out-of-the-box PPA with Intel 18A
PrimeClosure: Accelerating ECO Convergence with PrimeClosure Advanced Technologies
Improve CTS QoR by H-tree-only (Non-Mesh) Regular MSCTS for complex floorplans and notches design
Advanced Strategies and Recipes for High-Speed Non-Rectilinear Partition Convergence
Broadening the Horizon –AI-Driven Digital Design Exploration and Implementation
Establishing an End-To-End Methodology for Shield Reliability in Leading Tech Node PowerVIA Designs
3DIC Exploration, Implementation and System Analysis For Multi-Die Design
Flexible Hardware-assisted Verification Synopsys ZeBu EP platforms
Next-Generation Verdi: Overview ofthe IDE and the VerificationManagement System
Silicon.da Silicon Insights and Data Analytics from Design to Manufacturing
Performance Improvements at Full-Chip level using Elastic on Intel XEON designs
Automated Layout and Analysis for Optimization of Power MOSFETs Using PDG and R3D
RevolutionizingAdvanced Node Processes: Samsung Foundry Embraces Synopsys QuickCapfor SF2
ECO in the Age of AI: Advancing Signoff Convergence with PrimeClosure
Achieving Scalability in Transistor-level STA Synopsys NanoTime for DRAM Design
Understanding the UVM m_sequencer, p_sequencer Handles, and the uvm_declare_p_sequencer Macro
Next-Generation Verdi: Overview of New Debug andVerification Management
Automated Constraints Promotion Methodology from IP to SoC Designs for Complex Designs
Achieve First-pass Silicon with Efficient RTL to Gate Static Signoff Methodology Using VC SpyGlass
Towards Bug Free Application Specific Instruction-Set Processors (ASIPs) with Formal Verification
Advanced Formal Verification Methodologies for a Read-Only Cache with Out-of-Order Support
Comprehensive Verification and Performance Analysis of HBM3 Memory Subsystem
Optimizing Multi-protocol IEEE 802.3 PCS Verification with Synopsys Ethernet VIP
An early physical synthesis prototyping flow with RTL Architect
Using Synopsys Machine Learning and AI tools to optimize PPA with reduced designer effort
From Vision To Reality : SiMa.ai’s Physical Design Journey with Synopsys
Adoption of PATH MARGIN MONITOR (PMM) and Overcoming the Implementation Challenges in SoC Design
Closing Functional Coverage With Deep Reinforcement Learning A Compression Encoder Example
7NM SoC ESD & LUP reliability signoff usingIC Validator PERC
Advanced Implementation Techniques For Achieving Best PPA in High Performance Designs
Performing Functional ECO on Hierarchical Designs having Multiply Instantiated Modules
SAIF Based DPS and IRAP for Power and Power Grid Optimization for Complex IPs
Power Optimization Flows in Deep Sub-Micron Technologies for Computer Vision Systems
3D Process Simulation-Assisted Device Failure Analysis with Virtual Defect Injection in IC layout
Comprehensive IP Verification using Hybrid Way (simulation and formal) : User Experience
Multi Chip Simulation of Battery Management System with Synopsys Virtualizer Studio
Multi Chip Simulation of Battery Management System with Synopsys VirtualizerStudio
Using RTL Architect for Designing the Ultra-Low Power EdgeVision SoC
Using RTL Architect for Designing the Ultra-Low Power EdgeVisionSoC
Early power analysis flow using RTLA and RTL-PrimePower, with a focus on glitch power paper
Early power analysis flow using RTLA and RTL-PrimePower, with a focus on glitch power
Multi-Die Distributed Simulation -Next Generation Validation Framework
AI enabled coverage convergence acceleration for high-performance Visual Analytics core
Accelerating Pre-silicon Verification Efficiency through Innovative AI-Powered Debug Automation
Taking SDC Constraints to the Next Level with Timing Constraints Manager
Framework for Automated Connectivity Checks for core and SOCs
Application-level Hybrid Emulation for Software-Defined-Systems
Advancing Signoff Convergence with PrimeClosure in the age of AI
The PrimeClosure Paradigm:Next-Generation Tool For Enhanced TAT And ECO Fixing Rate
Enhancing Timing Signoff with Timing Constraint Manager: Case Study for SerDes and PCIe IPs
Towards Bug Free Application Specific Instruction-Set Processors (ASIPs) with Formal Verification
Maximizing Efficiency: Achieving Full Flat STA Run Overnight with Primetime Hypergrid
Forecasting the Timing and Static Power for Cells Arm perspective
Navigating Extraction and Timing Closure in Multi-Die System - ASignoff Methodology
Efficient methods to optimize PrimeTime-based full flat timing signoff runtime for large SoC designs
Enabling PCIe and NVMe pre-silicon validation with real devices using EP1 emulator
Efficient Verification Strategies to Accelerate Complex SoC Design Validation using ZeBu Emulator
Improving the DriverClk [Physical] Frequency of System Level Emulation Models
Accelerated Serial DFT SOC Scan Validation using ZeBuEmulator
Unlimited Possibility of AI: Automatic and Flexible Floorplan Shrinking Methodology by DSO.ai
Broadening the Horizon –AI-Driven Digital Design Exploration and Implementation
Enabling Next-Generation Advanced ASICs Using Synopsys high-speed interface IPs
AI-driven Memory Exploration in RTL Architect Efficient Physical-aware PPA Enhancement
PrimePower : Smart Pruner & Smart Partition of Concurrent-CAPP
PrimePowerCell EM(ElectroMigration) Analysis on Advanced Process
PowerReplay : Automated Name Mapping for DV Checker using PowerReplay
