gamegirl 【Done】

IC技术圈suisuisi

This open source project implements a fpga based (Nintendo Entertainment System) nes box.

YASA 【Done】

zhajio1988

YASA is an open source simulation framework for SystemVerilog/UVM testbentch released under the terms of Apache License, v. 2.0. It support mutli_simulators, multi_languages, lsf etc. It support several excellent features. Such as: customized command line arguments, can add any compilation options or simulation options, can running a testcase with random seeds for several rounds or running a group of testcases, each testcase has several command line options.

Open_RegModel 【Done】

zhajio1988

Use ORDT and systemRDL tools to generate C/Verilog header files, register RTL, UVM register models, and docs using SystemRDL.